1. Field of the Invention
Embodiments of the present invention generally relate to the fabrication of integrated circuits. More particularly, embodiments of the present invention relate to methods for forming silicon nitride hard masks.
2. Description of the Related Art
Integrated circuits have evolved into complex devices that can include millions of transistors, capacitors and resistors on a single chip. The evolution of chip designs continually requires faster circuitry and greater circuit density. The demands for faster circuits with greater circuit densities impose corresponding demands on the materials used to fabricate such integrated circuits.
The demands for greater integrated circuit densities also impose demands on the process sequences used for integrated circuit manufacture. For example, in process sequences using conventional lithographic techniques, a layer of energy sensitive resist, such as a photoresist, is formed over a stack of layers on a substrate. An image of a pattern is introduced into the energy sensitive resist layer. Then, the pattern introduced into the energy sensitive resist layer is transferred into one or more layers of the stack of layers formed on the substrate using the layer of energy sensitive resist as a mask. The pattern introduced into the energy sensitive resist can be transferred into one or more layers of the material stack using a chemical etchant. The chemical etchant is designed to have a greater etch selectivity for the material layers of the stack than for the energy sensitive resist. That is, the chemical etchant etches the one or more layers of the material stack at a much faster rate than it etches the energy sensitive resist. The faster etch rate for the one or more material layers of the stack typically prevents the energy sensitive resist material from being consumed prior to completion of the pattern transfer.
However, demands for greater circuit densities on integrated circuits have necessitated smaller pattern dimensions (e.g., sub-micron or nanometer dimensions). As the pattern dimensions are reduced, the thickness of the energy sensitive resist must correspondingly be reduced in order to control pattern resolution. Such thinner resist layers can be insufficient to mask underlying layers during a pattern transfer step using a chemical etchant.
An intermediate layer, called a hard mask, is often used between the energy sensitive resist layer and the underlying layers to facilitate pattern transfer into the underlying layers. Like the energy sensitive resist layers, hard mask layers must be more resistant to the etchant that is used to etch an underlying layer in order to prevent erosion of the hard mask before the etching of the underlying layer is completed.
Silicon nitride layers that can be used as hard masks have been developed. The silicon nitride layers are typically deposited by a thermal process in a furnace at a high temperature, such as 800° C. Such high temperatures are disadvantageous for processes with stringent thermal budget demands, such as in very large scale or ultra-large scale integrated circuit (VLSI or ULSI) device fabrication.
Thus, there remains a need for methods of depositing silicon nitride layers at lower temperatures, wherein the silicon nitride layers have etch rate properties that enable them to be used as hard mask layers.